The present invention relates to a semiconductor integrated circuit incorporating an SRAM (static radon-access memory).
As process rules for semiconductor integrated circuits have shrunk, transistors, mainly MOS (metal oxide semiconductor) transistors, have been decreased in area. This leads to lower cost resulting from a reduction in chip area, and to enhancement in transistor performance, and thus contributes to performance increase not only in LSIs (large-scale integration) alone but also in set equipment typified by mobile devices and other digital products. However, the shrinking process rules have produced adverse effects as well, such as an increase in variation in transistor characteristics. This is because the area occupied by a transistor has become extremely small, and thus variation in the transistor's impurity settings, shape, etc., has increased relatively.
It is known that the magnitude of variation in threshold value, which is one of the transistor characteristics, is proportional to 1/√(W×L) where W is the transistor width and L is the transistor length. That is, as a transistor is reduced in size, variation in the threshold voltage of the transistor is increased. Furthermore, as transistors have been miniaturized, the number of transistors mounted onto a single chip has been increased, causing effects of variation in transistor characteristics to become greater.
The performance of an SRAM memory cell can be indicated by the following three items: static noise margin, which shows the stability of memory data, cell current, which determines the performance at the time of read operation, and write margin, which determines the performance at the time of write operation. In order to ensure operation of an SRAM memory cell, conditions for all of these items must be satisfied. However these items are mutually contradictory, and thus if variation in transistor characteristics is large, it is quite difficult to satisfy conditions for all of these items in the entire variation range. Hence examining the characteristics of transistors on the chip is a step toward circuit improvements and is effective for the satisfaction of the specifications.
Variation roughly contains two kinds of components: a random component and a global component. The random component differs from transistor to transistor. The global component varies from one diffusion process to another and from one slice to another, for example. The random component occurs quite irregularly and is thus very difficult to control. Therefore, in circuit design, variation must be taken into account to keep a certain margin.
On the other hand, the global component gives the same tendency to the entire chip. If the precise value of this component is known, it is possible to effect circuit improvements. To that end, it is effective to measure the tendency of the characteristics of at least a certain number of transistors for each chip rather than measure the characteristics of individual transistors.
For example, Japanese Laid-Open Publication No. 2003-17540 discloses a method in which, mainly for a DRAM (dynamic random-access memory), the characteristics of transistors on a chip are externally evaluated by placing a probe to the source and drain regions of the transistors.
However, in the method disclosed in Japanese Laid-Open Publication No. 2003-17540, probe pads are provided on the chip and the transistor characteristics are measured in the chip fabrication stage. This causes a problem in that the fabrication process becomes complicated, and a region for the probing is separately needed. Furthermore, since the test process using the probe has to be performed before the completion of the chip, a problem in testing also occurs in that another flow is needed which is different from a chip testing process performed after the completion of the chip by using a tester.